MD Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason Bakos, Miaoqing Huang, and David Andrews, “FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul?” The 33rd International Conference on Field-Programmable Logic and Applications (FPL 2023), pp. 1-7, September 2023. arXiv
Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R.J. Downey, Jason D. Bakos, David Andrews, and Miaoqing Huang, “Accelerating LSTM-based High-Rate Dynamic System Models,” The 33rd International Conference on Field-Programmable Logic and Applications (FPL 2023), pp. 1-6, September 2023.
MD Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason Bakos, Miaoqing Huang, and David Andrews, “Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays,” The 31st IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM 2023), pp. 1-1, May 2023. IEEE
2022
T. Kamucheka, A. Nelson, D. Andrews and M. Huang, “A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm,” 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, 2022, pp. 1-1, IEEE
A. Panahi, E. Kabir, A. Downey, D. Andrews, M. Huang and J. D. Bakos, “High-Rate Machine Learning for Forecasting Time-Series Signals,” 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), New York City, NY, USA, 2022, pp. 1-9, IEEE
Kabir, E., Poudel, A., Aklah, Z., Huang, M., Andrews, D. (2022). A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA. In: Gan, L., Wang, Y., Xue, W., Chau, T. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2022. Lecture Notes in Computer Science, vol 13569. Springer, Cham. Springer
H. Liu, A. Panahi, D. Andrews and A. Nelson, “An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks,” in IEEE Sensors Journal, vol. 22, no. 4, pp. 3605-3615, 15 Feb.15, 2022, IEEE.
2021
A. Panahi, S. Balsalama, A. -T. Ishimwe, J. M. Mbongue and D. Andrews, “A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications,” 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 2021, pp. 24-27, IEEE.
Tendayi Kamucheka, Michael Fahr, Tristen Teague, Alexander Nelson, David Andrews, and Miaoqing Huang, “Power-based Side Channel Attack Analysis on PQC Algorithms”, Cryptology ePrint Archive, 2021 url
2020
S. Basalama, A. Panahi, A. -T. Ishimwe and D. Andrews, “SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices,” 2020 3rd International Conference on Data Intelligence and Security (ICDIS), South Padre Island, TX, USA, 2020, pp. 141-147, IEEE
H. Liu, A. Panahi, D. Andrews and A. Nelson, “FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks,” 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, AR, USA, 2020, pp. 225-225, IEEE
2019
A. Panahi, K. Stokke and D. Andrews, “A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs,” 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2019, pp. 1-8, IEEE
Hansmeier, T., Platzner, M., Pantho, M.J.H. et al. An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. J Sign Process Syst 91, 1259–1272 (2019). Journal of Signal Processing Systems
2018
M. J. H. Pantho, J. Mandebi Mbongue, C. Bobda and D. Andrews, “Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers,” 2018 International Conference on Field-Programmable Technology (FPT), Naha, Japan, 2018, pp. 342-345, IEEE
J. Mbongue, F. Hategekimana, D. Tchuinkou Kwadjo, D. Andrews and C. Bobda, “FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud,” 2018 IEEE 11th International Conference on Cloud Computing (CLOUD), San Francisco, CA, USA, 2018, pp. 862-865, IEEE
M. J. H. Pantho, J. M. Mbongue, C. Bobda, D. Andrews and M. Asadinia, “Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer,” 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, 2018, pp. 217-217, IEEE
Hansmeier, T., Platzner, M., Andrews, D. (2018). An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer
Sen Ma, Xuan Shi & David Andrews (2018) Parallelizing maximum likelihood classification (MLC) for supervised image classification by pipelined thread approach through high-level synthesis (HLS) on FPGA cluster, Big Earth Data, 2:2, 144-158, https://doi.org/10.1080/20964471.2018.1470249
2016
S. Ma, D. Andrews, S. Gao and J. Cummins, “Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud,” 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2016, pp. 1-6,IEEE
H. Ding, S. Ma, M. Huang and D. Andrews, “OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods,” 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Chicago, IL, USA, 2016, pp. 233-240, IEEE
Eugene Cartwright, “Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS)”, Ph.D. Dissertation at the University of Arkansas (May, 2016). Dissertation
Invited Talk “JIT Run Time Assembly of Hardware Accelerators”, Paderborn University, Paderborn Germany, June 30, 2016
Invited Paper David Andrews, Marco Platzner, “Programming Models for Reconfigurable Manycore Systems” Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) Tallinn, Estonia June 27-29, 2016 pp. 1-8 IEEE
S. Ma, Z. Aklah and D. Andrews, “Run time interpretation for creating custom accelerators,” 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2016, pp. 900-905 IEEE
Sen Ma, Zeyad Aklah, David Andrews, “Just In Time Assembly of Accelerators”, Proceedings of the 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016), Monterey California, February 21-23, 2016 pp. 173-178, https://arxiv.org/abs/1603.01187
Zeyad Aklah, Sen Ma and David Andrews, “A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators” 2nd International Workshop on Overlay Architectures for FPGAs (OLAF). Sunday workshop at the 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016) 2 page abstract.
2015
Sen Ma, Hongyuan Ding, Miaoqing Huang and David Andrews, “Archborn: An Open Source Tool for Automated Generation of Chip Heterogeneous Multiprocessor Architectures”, Proceedings of the International Conference on ReConFigurable Computing and FPGAs, Cancun Mexico, Dec 7-9, 2015
Nithin George, Hyoukloong Lee, David Novo, Muhsen Owaida, Davi Andrews, Kunle Olukotun, and Paolo Ienne,”Automatic Support for Multi-Module Parallelism from Computational Patterns”, Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) pp.93-100, London, England, 2015
Sen Ma, Zeyad Aklah and David Andrews, “A Run Time Interpretation Approach for Creating Custom Accelerators”, Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), pp.472-475, London, England, 2015
Paolo Ienne, David Andrews, Walid Najjar, Reconfigurable Computing for the Masses, Really ? Workshop at the 25th International Conference on Field Programmable Logic and Applications (FPL) London, England, 2015
David Andrews, Can We Finally Allow Software Programmers to Create Hardware Accelerators ? Invited Talk at ETH Zurich, April 30, 2015
Keynote Talk David Andrews, Will the future success of Reconfigurable Computing require a paradigm shift in our research communities thinking?, 11th International Symposium on Applied Reconfigurable Computing (ARC), Bochum Germany, April 16, 2015
Zeyad Aklah and David Andrews, “A Flexible Multilayer Perceptron Co-Processor for FPGAs” Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), pp. 427-434, Bochum Germany, April 13-17, 2015
2014
Cartwright, Eugene; Sadeghian, Alborz; Ma, Sen; Andrews, David, “Achieving Portability and Efficiency over Chip Heterogeneous Multiprocessor Systems,” Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, pp.1-4, 2-4 Sept. 2014
Sen Ma, David L. Andrews: On energy efficiency and Amdahl’s law in FPGA based chip heterogeneous multiprocessor systems (abstract only). FPGA 2014: 253
David Andrews, “Operating Systems Research for Reconfigurable Computing”, IEEE Micro, vol.34, no. 1, pp. 54-58, Jan.-Feb. 2014, doi:10.1109/MM.2014.1
2013
Gerard Allwein, William Harrison and David Andrews,Simulation Logic Journal of Logic and Logical Philosophy, DOI: 10.12775/LLP.2013.0127, September 2013
Miaoqing Huang and David Andrews, Modular Design of Fully Pipelined Reduction Circuits on FPGAs, IEEE Transactions on Parallel and Distributed Systems, Vol. 24, No 9., Sept. 2013, pp.1818-1826
2012
Sen Ma, Miaoqing Huang, David Andrews, Developing Application-Specific Multiprocessor Platforms on FPGAs, Poster session of Reconfig 2012
E. Cartwright, A. Fahkari, Sen Ma, C. Smith, M. Huang, D. Andrews, Jason Agron, Automating the Design of MLUT MPSOPC FPGA’s in the Cloud, Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012
Miaoqing Huang and Liang Men, Improving the Performance of On-Board Cache for Flash-based Solid-State Drives, in Proceedings of The 7th IEEE International Conference on Networking, Architecture, and Storage (NAS 2012), Xiamen, China, June 28-30, 2012.
D. Andrews, Visions for RC in the Next Twenty Years, Presentation at Sunday Workshop on Reconfigurable Computing and FCCM: What have we done in 20 years, and what will Reconfigurable Computing mean in 2032?, FCCM2012, April 2012.
Sen Ma, Miaoqing Huang, Eugene Cartwright, and David Andrews, Scalable Memory Hierarchies for Embedded Manycore Systems, in Proceedings of The 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), LNCS 7199, pp. 151-162, Hong Kong, China, March 19-23, 2012.
2011
J. Agron, D. Andrews, M. Happe, E. Lubbers, and M. Platzner, Multithreaded Programming of Reconfigurable Embedded Systems, in Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui and H.-M. Hanisch, Eds. Information Science Publishing, 2011, ch. 2, pp. 31–54.
Miaoqing Huang, Kris Gaj, and Tarek El-Ghazawi, New Hardware Architectures for Montgomery Modular Multiplication Algorithm, IEEE Transactions on Computers, vol. 60, no. 7, pp. 923-936, July 2011.
Ozlem Kilic, Miaoqing Huang, Charles Conner, and Mark S. Mirotznik, Hardware Accelerated Design of Millimeter Wave Antireflective Surfaces: A Comparison of Field-Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) Implementations, ACES (The Applied Computation Electromagnetics Society) Journal, vol. 26, no. 3, pp. 188-198, March 2011.
Liang Zhou, Miaoqing Huang, and Scott C. Smith, High-Performance and Area-Efficient Hardware Design for Radix-2^k Montgomery Multipliers, in Proceedings of The 2011 International Conference on Computer Design (CDES’11), Las Vegas, USA, July 18-21, 2011.
David Andrews, Design Flows and Run Time Systems for Heterogeneous Multiprocessor Systems on Programmable Chips (MPSoPCs), Printed abstract in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, USA, July 18-21, 2011 pp.253-254
Lingyuan Wang, Miaoqing Huang, and Tarek El-Ghazawi, Exploiting Concurrent Kernel Execution on Graphic Processing Units, in Proceedings of The 2011 International Conference on High Performance Computing & Simulation (HPCS 2011), pp. 24-32, Istanbul, Turkey, July 4-8, 2011. (Acceptance ratio: 48/171=28.07%)
Eugene Cartwright, Sen Ma, David Andrews, and Miaoqing Huang, Creating HW/SW Co-Designed MPSoPC’s from High Level Programming Models, in Proceedings of Workshop on Multiprocessor Systems on (Programmable) Chips (MPSoC 2011) as part of The 2011 International Conference on High Performance Computing & Simulation (HPCS 2011), pp. 554-560, Istanbul, Turkey, July 4-8, 2011.
Lingyuan Wang, Miaoqing Huang, Vikram K. Narayana, and Tarek El-Ghazawi, Scaling Scientific Applications on Clusters of Hybrid Multicore/GPU Nodes, in Proceedings of The 8th ACM International Conference on Computing Frontiers (CF’11), Ischia, Italy, May 3-5, 2011. (Acceptance ratio: 22/101=21.8%)
Jorge Ortiz and David Andrews, A Streaming High-Throughput Linear Sorter System with Contention Buffering, International Journal of Reconfigurable Computing, vol. 2011, Article ID 963539, 12 pages, 2011. doi:10.1155/2011/963539
2010
Miaoqing Huang, David Andrews, and Jason Agron, “Operating System Structures for Multiprocessor Systems on Programmable Chip,” in Proceedings of 2010 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2010), Cancun, Mexico, Dec. 13-15, 2010.
David Andrews, Building Heterogeneous Systems With a Hardware Microkernel Presentation given at Xilinx, San Jose, California, August 16, 2010
Miaoqing Huang and David Andrews, Modular Design of Fully Pipelined Accumulators, in Proceedings of The 2010 International Conference on Field-Programmable Technology (FPT’10), Beijing, China, Dec. 8-10, 2010.
Jason Agron, Hardware Microkernels - A Novel Method for Constructing Operating Systems for Heterogeneous Multi-Core Platforms, Ph.D. Dissertation at the University of Arkansas (August, 2010). Dissertation and Presentation Slides.
David Andrews, Christian Plessl, Configurable Processor Architectures: History and Trends, Abstract of Invited Talk in Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, Nevada USA, July 12-15, 2010
Miaoqing Huang, Lingyuan Wang, and Tarek El-Ghazawi, “Accelerating Double Precision Floating-point Hessenberg Reduction on FPGA and Multicore Architectures,” in Proceedings of 2010 Symposium on Application Accelerators in High Performance Computing (SAAHPC’10), Knoxville, Tennessee, USA, July 13-15, 2010.
David Andrews, Reconfigurable Architectures in the Heterogeneous Manycore Era, Proceedings of the 8th International Conference on High Performance Computing and Simulation (HPCS2010), Keynote Speech in the Special Session on Embedded and Reconfigurable Computing (ERC2010) Caen France, June 28-July 2, 2010
Miaoqing Huang, Olivier Serres, Vikram K. Narayana, Tarek El-Ghazawi, and Gregory Newby, “Efficient Cache Design for Solid-State Drives,” in Proceedings of The ACM International Conference on Computing Frontiers 2010 (CF’10), pp. 41-50, Bertinoro, Italy, May 17-19, 2010. (Acceptance ratio: 30/113=26.5%)
Jason Agron and David Andrews, Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality A System Primitive, Proceedings of The 18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Charlotte, North Carolina. May 2-4, 2010.
Miaoqing Huang and Ozlem Kilic, “Reaping the processing potential of FPGA on double-precision floating-point operations: an eigenvalue solver case study,” in Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), pp. 95-102, Charlotte, North Carolina, USA, May 2-4, 2010. (Acceptance ratio: 24/132=18.2%)
Ozlem Kilic, Miaoqing Huang, Charles Conner, and Mark S. Mirotznik, “Hardware Accelerated Design of Millimeter Wave Antireflective Surfaces,” in Proceedings of the 26th ACES Conference (ACES 2010), Tampere, Finland, April 25-29, 2010.
Jorge Ortiz and David Andrews, A Configurable High-Throughput Linear Sorter System , Proceedings of the 17th Reconfigurable Architectures Workshop (RAW) at International Symposium on Parallel and Distributed Systems (IPDPS), Atlanta, Georgia April 19-23, 2010 Presentation (PDF)
Ozlem Kilic and Miaoqing Huang, “Overview of Reconfigurable Computing Platforms and Their Applications in Electromagnetics Applications”, ACES (The Applied Computation Electromagnetics Society) Journal, vol.25, no.4, pp.283-293, April, 2010.
Miaoqing Huang, Olivier Serres, and Tarek El-Ghazawi, and Gregory Newby, “Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study,” International Journal of Reconfigurable Computing, vol.2010, pp.1-11, April, 2010, doi:10.1155/2010/454506.
Jason Agron and David Andrews, Efficient OS Services for Heterogeneous and Reconfigurable Manycores, Proceedings of the Many-Core and Reconfigurable Supercomputing Conference (MRSC’2010), Rome, Italy.
2009
Jason Agron and David Andrews, Building Heterogeneous Reconfigurable Systems With a Hardware Microkernel. Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS, Grenoble, France, October 2009. Presentation (PDF)
Jason Agron and David Andrews, Hardware Microkernels for Heterogeneous Manycore Systems. Proceedings of the First International Workshop on Real-time Systems on Multicore Platforms: Theory and Practice (XRTS) held in conjunction with the 38th International Conference on Parallel Processing (ICPP), Vienna, Austria, September 2009.
Jason Agron and David Andrews, Building Heterogeneous Reconfigurable Systems Using Threads. Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, September 2009.
Teng Li, Miaoqing Huang, Tarek El-Ghazawi, and H. Howie Huang, “Reconfigurable Active Disk: An FPGA Accelerated Storage Architecture for Data-Intensive Applications,” in Proceedings of 2009 Symposium on Application Accelerators in High-Performance Computing (SAAHPC’09), Urbana, Illinois, USA, July 28-30, 2009.
Jason Agron, Domain-Specific Language for HW/SW Co-Design for FPGAs (PRE-PRINT). Proceedings of the IFIP Working Conference on Domain Specific Languages (DSL WC), Volume 5658 of Lecture Notes in Computer Science, pages 262-284. Springer-Verlag, July, 2009.
William Harrison, Adam Procter, Jason Agron, Garrin Kimmell, and Gerard Allwein, Model-driven Engineering from Modular Monadic Semantics: Implementation Techniques Targeting Hardware and Software (PRE-PRINT). Proceedings of the IFIP Working Conference on Domain Specific Languages (DSL WC), Volume 5658 of Lecture Notes in Computer Science, pages 20-44. Springer-Verlag, July, 2009.
Jason Agron and David Andrews, Hardware Microkernels for Heterogeneous Manycore Systems. Proceedings of the Fifth International Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT), Dublin, Ireland, June, 2009.
Miaoqing Huang, Harald Simmler, Olivier Serres, and Tarek El-Ghazawi, “RDMS: A Hardware Task Scheduling Algorithm for Reconfigurable Computing,” in Proceedings of the 16th Reconfigurable Architectures Workshop (RAW 2009), Rome, Italy, May 25-26, 2009.
Miaoqing Huang, Vikram K. Narayana, and Tarek El-Ghazawi, “Efficient mapping of hardware tasks on reconfigurable computers using libraries of architecture variants,” in Proceedings of the Seventeenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’09), pp. 247-250, Napa, CA, USA, April 5-7, 2009.
Miaoqing Huang, Olivier Serres, Tarek El-Ghazawi, and Greg Newby, “Parameterized Hardware Design on Reconfigurable Computers: An Image Registration Case Study”, in Proceedings of V Southern Conference on Programmable Logic (SPL 2009), pp.71-76, Sao Carlos, Brazil, April 1-3, 2009.
2008
D. Andrews, Increasing Design Productivity for Next Generation Platform FPGA’s , Presentation at the ICFPT08 Pre-Workshop on FPGA Design Productivity, December 2008
Miaoqing Huang, Harald Simmler, Proshanta Saha, and Tarek El-Ghazawi, “Hardware Task Scheduling Optimizations for Reconfigurable Computing,” in Proceedings of the Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA’08), Austin, Texas, USA, Nov. 17, 2008.
Miaoqing Huang, Olivier Serres, Tarek El-Ghazawi, and Greg Newby, “Implementing Image Registration Algorithms on Reconfigurable Computer,” in Proceedings of 10th Military and Aerospace Programmable Logic Devices Conference (MAPLD 2008), Annapolis, Maryland, USA, Sept. 15-18, 2008.
D. Andrews, J. Agron, Modeling Abstractions for Next-Generation Reconfigurable Computing, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) July 2008
Miaoqing Huang, Ivan Gonzalez, Sergio Lopez-Buedo, and Tarek El-Ghazawi, “A Framework to Improve IP Portability on Reconfigurable Computers,” in Proceedings of The 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2008), pp.191-197, Las Vegas, Nevada, USA, July 14-17, 2008.
Miaoqing Huang, Esam El-Araby, and Tarek El-Ghazawi, “Divide-and-Conquer Approach for Designing Large-operand Functions on Reconfigurable Computers,” in Proceedings of the 4th Reconfigurable Systems Summer Institute, 2008 (RSSI’08), Urbana, Illinois, USA, July 7-9, 2008.
Santner, S., Peck, W., Agron, J., and Andrews, D., Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs, Proceedings of the 4th International Workshop on Applied Reconfigurable Computing (ARC 2008) in Lecture Notes in Computer Science, Springer-Verlag, Number 4943, pp. 99 - 110, 2008
Proshanta Saha, Esam El-Araby, Miaoqing Huang, Mohamed Taher, Sergio Lopez-Buedo,Tarek El-Ghazawi, Chang Shu, Kris Gaj, Alan Michalski, and Duncan Buell, “Portable library development for reconfigurable computing systems: A case study,” Parallel Computing, vol.34, no.4+5, pp.245-260, May, 2008.
Elias Teodoro Silva Jr., David Andrews, Carlos Eduardo Pereira, and Flavio Rech Wagner An Infrastructure for Hardwdare-Software Co-Design of Embedded Real-Time Java Applications, Proceedings of the 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008) pp. 273-280, May 2008.
Miaoqing Huang, Olivier Serres, Sergio Lopez-Buedo, Tarek El-Ghazawi, and Greg Newby, “An Image Processing Architecture To Exploit I/O Bandwidth on Reconfigurable Computers,” in Proceedings of IEEE IV Southern Conferece on Programmable Logic (SPL 2008), pp.257-260, Bariloche-Patagonia, Argentina, March 26-28, 2008.
Miaoqing Huang, Kris Gaj, Soonhak Kwon, and Tarek El-Ghazawi, “An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm,” in Proceedings of The 11th International Workshop on Practice and Theory in Public Key Cryptography (PKC 2008), LNCS vol.4939, pp.214-228, March 9-12, 2008.
Tarek El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr Kindratenko, and Duncan Buell, “The promise of high-performance reconfigurable computing,” IEEE Computer, vol.41, no.2, pp.69-76, Feb. 2008.
D. Andrews, R. Sass, E. Anderson, J. Agron, W. Peck, J. Stevens, F. Baijot, and E. Komp, Achieving Programming Model Abstractions For Reconfigurable Computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 34–44, January 2008.
2007
Miaoqing Huang, Ivan Gonzalez, and Tarek El-Ghazawi, “A Portable Memory Access Framework on Reconfigurable Computers,” in Proceedings of IEEE 2007 International Conference on Field-Programmable Technology (ICFPT’07), pp. 333-336, December 12-14, 2007.
Thamer Abuyasin, Enabling Task Level Parallelism In Handel-C, Master’s Thesis at the University of Kansas (December, 2007). Thesis and presentation slides.
Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, and David Andrews, Supporting High-Level Language Semantics Within Hardware Resident Threads, 17th International Conference on Field Programmable Logic and Applications, August 2007. pp. 98-103.
Jim Stevens, Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C, Ph.D. Forum at the 17th International Conference on Field Programmable Logic and Applications, August 2007.
Erik Anderson, Abstracting the Hardware/Software Boundary through a Standard System Support Layer and Architecture, Ph.D. Dissertation at the University of Kansas (May, 2007). Thesis and presentation slides.
Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, and David Andrews, Memory Hierarchy for MCSoPC Multithreaded Systems, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2007.
Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka, Kushal Datta, David Andrews, Richard S. Miller, and Daniel Stanzione, Jr. Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing, Proceedings of the Fifteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA. April 2007.
Miaoqing Huang, Tarek El-Ghazawi, Brian Larson, and Kris Gaj, “Development of Block-Cipher Library for Reconfigurable Computers,” in Proceedings of IEEE III Southern conference on Programmable Logic (SPL 2007), pp.191-194, February 26-28, 2007.
2006
Jason Agron, Wesley Peck, Erik Anderson, David Andrews, Ed Komp, Ron Sass, Fabrice Baijot, and Jim Stevens, Run-Time Services for Hybrid CPU/FPGA Systems on Chip, Proceedings of the 27th IEEE International Real-Time Systems Symposium, Rio De Janeiro, Brazil, December 2006 pp. 3 - 12. File:Rtss06.pdf
Wesley Peck, Erik Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, and David Andrews, Hthreads: A Computational Model for Reconfigurable Devices, Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) August 2006. pp. 885-888 File:Fpl06.pdf
David Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot and Ed Komp,, The Case for High level Programming Models for Reconfigurable Computers, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2006. File:Ersa06.pdf
Jason Agron, Run-Time Scheduling Support for Hybrid CPU/FPGA SoCs, Master’s Thesis at the University of Kansas (April, 2006). Thesis and presentation Slides
Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews, Enabling a Uniform Programming Model Across the Software/Hardware Boundary, Proceedings of The Fourteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, 24-26 April 2006. File:Fccm06.pdf
2005
Razali Jidin, Extending the Thread Programming Model Across Hybrid FPGA/CPU Architectures, Ph.D. Dissertation at the University of Kansas (April, 2005). Thesis and presentations slides
David Andrews, Wesley Peck, Jason Agron, Keith Preston, Ed Komp, Mike Finley, Ron Sass, hthreads: A Hardware/Software Co-Designed Multithreaded RTOS Kernel, Proceedings of the 10th IEEE International Conference on Emerging Technologies and Factory Automation Facolta’ di Ingegneria, Catania, Italy, 19-22 September 2005. File:Etfa05.pdf
David Andrews, Iain Bate, Thomas Nolte, Clara M. Otero Perez, Stefan M. Petters, Impact of Embedded Systems Evolution on RTOS Use and Design, Proceedings of the 1st International Workshop Operating System Platforms for Embedded Real-Time Applications (OSPERT’05) in conjunction with the 17th Euromicro International Conference on Real-Time Systems (ECRTS’05), p 13-19, Palma de Mallorca, Balearic Islands, Spain. File:Ospert.pdf
R. Jidin, D. Andrews, W. Peck, D. Chirpich, K. Stout, J. Gauch, Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transform, Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), April 4-5, 2005, Denver, Colorado, USA. File:Hwimage.pdf
2004
W. Peck, J. Agron, D. Andrews, M. Finley, E. Komp, Hardware/Software Co-Design of Operating System Services for Thread Management and Scheduling, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. File:RTSS wesley.pdf
J. Agron, D. Andrews, M. Finley, E. Komp, W. Peck, FPGA Implementation of a Priority Scheduler Module, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. File:RTSS FPGA Scheduler.pdf
R. Jidin, D. Andrews, D. Niehaus, W. Peck, Fast Synchronization Primitives for Hybrid CPU/FPGA Multithreading, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. Online Proceedings (Pages 27-31)
Andrews, D., Niehaus, D., Jidin, R., Finley, M., Peck, W., Frisbee, M., Ortiz, J. Komp, E., Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components: A Missing Link, IEEE Micro, July/August 2004. File:Micro.pdf
Jidin, R., Andrews, D., Niehaus, D., Implementing Multi Threaded System Support for Hybrid Computational Components, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2004, Las Vegas, Nevada. File:ERSA2004.pdf
Andrews, D., Niehaus, D., Jidin, R., Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Components, Proceedings of the 1st Workshop on Embedded Processor Architectures (WEPA) held in conjunction with the International Symposium on Computer Architecture, February, 2004, Madrid, Spain. File:Wepa.pdf
Andrews, D., Niehaus, D., and Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components, IEEE Computer, January 2004. File:Computer.pdf
Michael Finley, Hardware/Software Codesign: Thread Manager, Master’s Thesis at the University of Kansas (December, 2004). Thesis and presentation slides
2003
Niehaus, D. , Andrews, D., Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation, Proceedings of the 9th International Workshop on Object-oriented Real-time Dependable Systems (WORDS 2003). File:Ku-words.pdf
David Andrews and Douglas Niehaus, Architectural Frameworks for MPP System on a Chip, Proceedings of the Third Workshop on Massively Parallel Processing (MPP), April 2003, Nice, France. File:Mpp.pdf