#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XBRAM_NUM_INSTANCES 1

/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_COMPATIBLE "xlnx,lmb-bram-if-cntlr-4.0"
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x1ffff
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 0x20
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0x0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 0x1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 0x2

/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_XBRAM_0_BASEADDR 0x0
#define XPAR_XBRAM_0_HIGHADDR 0x1ffff
#define XPAR_XBRAM_0_COMPATIBLE "xlnx,lmb-bram-if-cntlr-4.0"
#define XPAR_XBRAM_0_CE_FAILING_REGISTERS 0x0
#define XPAR_XBRAM_0_DATA_WIDTH 0x20
#define XPAR_XBRAM_0_ECC 0x0
#define XPAR_XBRAM_0_ECC_ONOFF_REGISTER 0x0
#define XPAR_XBRAM_0_ECC_ONOFF_RESET_VALUE 0x1
#define XPAR_XBRAM_0_FAULT_INJECT 0x0
#define XPAR_XBRAM_0_UE_FAILING_REGISTERS 0x0
#define XPAR_XBRAM_0_WRITE_ACCESS 0x2

#define XPAR_XGPIO_NUM_INSTANCES 3

/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_AXI_GPIO_0_BASEADDR 0x40000000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4000ffff
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0x1
#define XPAR_AXI_GPIO_0_IS_DUAL 0x1
#define XPAR_AXI_GPIO_0_INTERRUPTS 0x2002
#define XPAR_FABRIC_AXI_GPIO_0_INTR 2
#define XPAR_AXI_GPIO_0_INTERRUPT_PARENT 0x41200001
#define XPAR_AXI_GPIO_0_GPIO_WIDTH 0x4

/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_XGPIO_0_BASEADDR 0x40000000
#define XPAR_FABRIC_XGPIO_0_INTR 2
#define XPAR_XGPIO_0_HIGHADDR 0x4000ffff
#define XPAR_XGPIO_0_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_XGPIO_0_GPIO_WIDTH 0x4
#define XPAR_XGPIO_0_INTERRUPT_PRESENT 0x1
#define XPAR_XGPIO_0_IS_DUAL 0x1
#define XPAR_XGPIO_0_INTERRUPTS 0x2002
#define XPAR_XGPIO_0_INTERRUPT_PARENT 0x41200001

/* Definitions for peripheral AXI_GPIO_1 */
#define XPAR_AXI_GPIO_1_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_AXI_GPIO_1_BASEADDR 0x40010000
#define XPAR_AXI_GPIO_1_HIGHADDR 0x4001ffff
#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0x0
#define XPAR_AXI_GPIO_1_IS_DUAL 0x1
#define XPAR_AXI_GPIO_1_GPIO_WIDTH 0xc

/* Canonical definitions for peripheral AXI_GPIO_1 */
#define XPAR_XGPIO_1_BASEADDR 0x40010000
#define XPAR_XGPIO_1_HIGHADDR 0x4001ffff
#define XPAR_XGPIO_1_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_XGPIO_1_GPIO_WIDTH 0xc
#define XPAR_XGPIO_1_INTERRUPT_PRESENT 0x0
#define XPAR_XGPIO_1_IS_DUAL 0x1

/* Definitions for peripheral AXI_GPIO_2 */
#define XPAR_AXI_GPIO_2_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_AXI_GPIO_2_BASEADDR 0x40020000
#define XPAR_AXI_GPIO_2_HIGHADDR 0x4002ffff
#define XPAR_AXI_GPIO_2_INTERRUPT_PRESENT 0x1
#define XPAR_AXI_GPIO_2_IS_DUAL 0x1
#define XPAR_AXI_GPIO_2_INTERRUPTS 0x2003
#define XPAR_FABRIC_AXI_GPIO_2_INTR 3
#define XPAR_AXI_GPIO_2_INTERRUPT_PARENT 0x41200001
#define XPAR_AXI_GPIO_2_GPIO_WIDTH 0x20

/* Canonical definitions for peripheral AXI_GPIO_2 */
#define XPAR_XGPIO_2_BASEADDR 0x40020000
#define XPAR_FABRIC_XGPIO_2_INTR 3
#define XPAR_XGPIO_2_HIGHADDR 0x4002ffff
#define XPAR_XGPIO_2_COMPATIBLE "xlnx,axi-gpio-2.0"
#define XPAR_XGPIO_2_GPIO_WIDTH 0x20
#define XPAR_XGPIO_2_INTERRUPT_PRESENT 0x1
#define XPAR_XGPIO_2_IS_DUAL 0x1
#define XPAR_XGPIO_2_INTERRUPTS 0x2003
#define XPAR_XGPIO_2_INTERRUPT_PARENT 0x41200001

#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral AXI_INTC_0 */
#define XPAR_AXI_INTC_0_COMPATIBLE "xlnx,axi-intc-4.1"
#define XPAR_AXI_INTC_0_BASEADDR 0x41200000
#define XPAR_AXI_INTC_0_HIGHADDR 0x4120ffff
#define XPAR_AXI_INTC_0_KIND_OF_INTR 0x1
#define XPAR_AXI_INTC_0_IS_FAST 0x0
#define XPAR_AXI_INTC_0_IVAR_RST_VAL 0x10
#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 0x4
#define XPAR_AXI_INTC_0_ADDR_WIDTH 0x20
#define XPAR_AXI_INTC_0_NUM_SW_INTR 0x0
#define XPAR_AXI_INTC_0_HAS_IVR 0x1
#define XPAR_AXI_INTC_0_HAS_CIE 0x1
#define XPAR_AXI_INTC_0_HAS_SIE 0x1
#define XPAR_AXI_INTC_0_HAS_IPR 0x1

/* Canonical definitions for peripheral AXI_INTC_0 */
#define XPAR_XINTC_0_BASEADDR 0x41200000
#define XPAR_XINTC_0_HIGHADDR 0x4120ffff
#define XPAR_XINTC_0_ADDR_WIDTH 0x20
#define XPAR_XINTC_0_COMPATIBLE "xlnx,axi-intc-4.1"
#define XPAR_XINTC_0_HAS_IVR 0x1
#define XPAR_XINTC_0_HAS_CIE 0x1
#define XPAR_XINTC_0_HAS_SIE 0x1
#define XPAR_XINTC_0_HAS_IPR 0x1
#define XPAR_XINTC_0_IS_FAST 0x0
#define XPAR_XINTC_0_IVAR_RST_VAL 0x10
#define XPAR_XINTC_0_KIND_OF_INTR 0x1
#define XPAR_XINTC_0_NUM_INTR_INPUTS 0x4
#define XPAR_XINTC_0_NUM_SW_INTR 0x0

#define XPAR_XSPI_NUM_INSTANCES 1

/* Definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_AXI_QUAD_SPI_0_COMPATIBLE "xlnx,axi-quad-spi-3.2"
#define XPAR_AXI_QUAD_SPI_0_BASEADDR 0x44a40000
#define XPAR_AXI_QUAD_SPI_0_HIGHADDR 0x44a4ffff
#define XPAR_AXI_QUAD_SPI_0_HASFIFOS 0x1
#define XPAR_AXI_QUAD_SPI_0_SLAVEONLY 0x0
#define XPAR_AXI_QUAD_SPI_0_NUM_SS_BITS 0x1
#define XPAR_AXI_QUAD_SPI_0_BITS_PER_WORD 0x8
#define XPAR_AXI_QUAD_SPI_0_SPI_MODE 0x2
#define XPAR_AXI_QUAD_SPI_0_AXI_INTERFACE 0x0
#define XPAR_AXI_QUAD_SPI_0_AXI4_ADDRESS 0x0
#define XPAR_AXI_QUAD_SPI_0_XIP_MODE 0x0
#define XPAR_AXI_QUAD_SPI_0_FIFO_SIZE 0x10

/* Canonical definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_XSPI_0_AXI4_ADDRESS 0x0
#define XPAR_XSPI_0_BASEADDR 0x44a40000
#define XPAR_XSPI_0_HIGHADDR 0x44a4ffff
#define XPAR_XSPI_0_AXI_INTERFACE 0x0
#define XPAR_XSPI_0_BITS_PER_WORD 0x8
#define XPAR_XSPI_0_COMPATIBLE "xlnx,axi-quad-spi-3.2"
#define XPAR_XSPI_0_FIFO_SIZE 0x10
#define XPAR_XSPI_0_HASFIFOS 0x1
#define XPAR_XSPI_0_NUM_SS_BITS 0x1
#define XPAR_XSPI_0_SLAVEONLY 0x0
#define XPAR_XSPI_0_SPI_MODE 0x2
#define XPAR_XSPI_0_XIP_MODE 0x0

#define XPAR_XTMRCTR_NUM_INSTANCES 1

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_COMPATIBLE "xlnx,axi-timer-2.0"
#define XPAR_AXI_TIMER_0_BASEADDR 0x41c00000
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41c0ffff
#define XPAR_AXI_TIMER_0_CLOCK_FREQUENCY 0x4d7bee1
#define XPAR_AXI_TIMER_0_INTERRUPTS 0x2001
#define XPAR_FABRIC_AXI_TIMER_0_INTR 1
#define XPAR_AXI_TIMER_0_INTERRUPT_PARENT 0x41200001

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_XTMRCTR_0_BASEADDR 0x41c00000
#define XPAR_FABRIC_XTMRCTR_0_INTR 1
#define XPAR_XTMRCTR_0_HIGHADDR 0x41c0ffff
#define XPAR_XTMRCTR_0_COMPATIBLE "xlnx,axi-timer-2.0"
#define XPAR_XTMRCTR_0_CLOCK_FREQUENCY 0x4d7bee1
#define XPAR_XTMRCTR_0_INTERRUPTS 0x2001
#define XPAR_XTMRCTR_0_INTERRUPT_PARENT 0x41200001

#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_COMPATIBLE "xlnx,axi-uartlite-2.0"
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060ffff
#define XPAR_AXI_UARTLITE_0_BAUDRATE 0x1c200
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0x0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0x0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 0x8
#define XPAR_AXI_UARTLITE_0_INTERRUPTS 0x0
#define XPAR_FABRIC_AXI_UARTLITE_0_INTR 0
#define XPAR_AXI_UARTLITE_0_INTERRUPT_PARENT 0x41200001

/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_XUARTLITE_0_BASEADDR 0x40600000
#define XPAR_FABRIC_XUARTLITE_0_INTR 0
#define XPAR_XUARTLITE_0_HIGHADDR 0x4060ffff
#define XPAR_XUARTLITE_0_BAUDRATE 0x1c200
#define XPAR_XUARTLITE_0_COMPATIBLE "xlnx,axi-uartlite-2.0"
#define XPAR_XUARTLITE_0_DATA_BITS 0x8
#define XPAR_XUARTLITE_0_INTERRUPTS 0x0
#define XPAR_XUARTLITE_0_INTERRUPT_PARENT 0x41200001
#define XPAR_XUARTLITE_0_ODD_PARITY 0x0
#define XPAR_XUARTLITE_0_USE_PARITY 0x0

/* Definitions for peripheral PMOD_DHB1_0 */
#define XPAR_PMOD_DHB1_0_BASEADDR 0x44a00000
#define XPAR_PMOD_DHB1_0_HIGHADDR 0x44a0ffff

/* Definitions for peripheral PMOD_DUAL_MAXSONAR_0 */
#define XPAR_PMOD_DUAL_MAXSONAR_0_BASEADDR 0x44a30000
#define XPAR_PMOD_DUAL_MAXSONAR_0_HIGHADDR 0x44a3ffff

/*  BOARD definition */
#define XPS_BOARD_ARTY-A7-100

#define XPAR_MIG_0_BASEADDRESS 0x80000000
#define XPAR_MIG_0_HIGHADDRESS 0x8fffffff
#define XPAR_LMB_BRAM_0_BASEADDRESS 0x0
#define XPAR_LMB_BRAM_0_HIGHADDRESS 0x1ffff

/*  CPU parameters definition */
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_EXCEPTIONS_IN_DELAY_SLOTS 1
#define XPAR_MICROBLAZE_FREQ 81247969
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_D_CACHE_LINE_SIZE 16
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_D_CACHE_SIZE 4096
#define XPAR_MICROBLAZE_I_CACHE_LINE_SIZE 16
#define XPAR_MICROBLAZE_I_CACHE_SIZE 4096
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 1
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 4096
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 4096
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_TIMEBASE_FREQUENCY 81247969
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 1
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER2 0
#define XPAR_MICROBLAZE_RESET_MSR 0
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_DCACHE 0
#define XPAR_MICROBLAZE_USE_DIV 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_HW_MUL 1
#define XPAR_MICROBLAZE_USE_ICACHE 0
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_D_CACHE_BASEADDR 0
#define XPAR_MICROBLAZE_D_CACHE_HIGHADDR 1073741823
#define XPAR_MICROBLAZE_I_CACHE_BASEADDR 0
#define XPAR_MICROBLAZE_I_CACHE_HIGHADDR 1073741823
#define XPAR_MICROBLAZE_REG 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 81247969

#define XPAR_MICROBLAZE_DDR_RESERVE_SA 0

#define XPAR_MICROBLAZE_ADDR_SIZE 32

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

/* Device ID */
#define XPAR_DEVICE_ID "7a100t"

#endif  /* end of protection macro */