/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2022, Xilinx, Inc.
 * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
 */

#ifndef _DT_BINDINGS_VERSAL2_POWER_H
#define _DT_BINDINGS_VERSAL2_POWER_H

#include "xlnx-versal-net-power.h"

#define PM_DEV_CAN_FD_2				(0x1822411DU)
#define PM_DEV_CAN_FD_3				(0x1822411EU)
#define PM_DEV_I2C_2				(0x18224117U)
#define PM_DEV_I2C_3				(0x18224118U)
#define PM_DEV_I2C_4				(0x18224119U)
#define PM_DEV_I2C_5				(0x1822411AU)
#define PM_DEV_I2C_6				(0x1822411BU)
#define PM_DEV_I2C_7				(0x1822411CU)
#define PM_DEV_TTC_4				(0x1822411FU)
#define PM_DEV_TTC_5				(0x18224120U)
#define PM_DEV_TTC_6				(0x18224121U)
#define PM_DEV_TTC_7				(0x18224122U)
#define PM_DEV_UFS				(0x18224116U)

#define PM_DEV_RPU_A_0				(0x181100BFU)
#define PM_DEV_RPU_A_1				(0x181100C0U)
#define PM_DEV_RPU_B_0				(0x181100C1U)
#define PM_DEV_RPU_B_1				(0x181100C2U)
#define PM_DEV_RPU_C_0				(0x181100F1U)
#define PM_DEV_RPU_C_1				(0x181100F2U)
#define PM_DEV_RPU_D_0				(0x181100F3U)
#define PM_DEV_RPU_D_1				(0x181100F4U)
#define PM_DEV_RPU_E_0				(0x181100F5U)
#define PM_DEV_RPU_E_1				(0x181100F6U)
#define PM_DEV_MMI_USB_DRD			(0x18224135U)
#define PM_DEV_MMI_GPU				(0x18224136U)
#define PM_DEV_MMI_DC				(0x18224137U)
#define PM_DEV_MMI_HDCP				(0x18224138U)
#define PM_DEV_MMI_DP				(0x18224139U)

#define PM_DEV_TCM_A_0A				(0x183180CBU)
#define PM_DEV_TCM_A_0B				(0x183180CCU)
#define PM_DEV_TCM_A_0C				(0x183180CDU)
#define PM_DEV_TCM_A_1A				(0x183180CEU)
#define PM_DEV_TCM_A_1B				(0x183180CFU)
#define PM_DEV_TCM_A_1C				(0x183180D0U)
#define PM_DEV_TCM_B_0A				(0x183180D1U)
#define PM_DEV_TCM_B_0B				(0x183180D2U)
#define PM_DEV_TCM_B_0C				(0x183180D3U)
#define PM_DEV_TCM_B_1A				(0x183180D4U)
#define PM_DEV_TCM_B_1B				(0x183180D5U)
#define PM_DEV_TCM_B_1C				(0x183180D6U)
#define PM_DEV_TCM_C_0A				(0x18318100U)
#define PM_DEV_TCM_C_0B				(0x18318101U)
#define PM_DEV_TCM_C_0C				(0x18318102U)
#define PM_DEV_TCM_C_1A				(0x18318103U)
#define PM_DEV_TCM_C_1B				(0x18318104U)
#define PM_DEV_TCM_C_1C				(0x18318105U)
#define PM_DEV_TCM_D_0A				(0x18318106U)
#define PM_DEV_TCM_D_0B				(0x18318107U)
#define PM_DEV_TCM_D_0C				(0x18318108U)
#define PM_DEV_TCM_D_1A				(0x18318109U)
#define PM_DEV_TCM_D_1B				(0x1831810AU)
#define PM_DEV_TCM_D_1C				(0x1831810BU)
#define PM_DEV_TCM_E_0A				(0x1831810CU)
#define PM_DEV_TCM_E_0B				(0x1831810DU)
#define PM_DEV_TCM_E_0C				(0x1831810EU)
#define PM_DEV_TCM_E_1A				(0x1831810FU)
#define PM_DEV_TCM_E_1B				(0x18318110U)
#define PM_DEV_TCM_E_1C				(0x18318111U)

#endif
