EECS 40103/50103 Domain Specific Architectures
Table of contents
- Introduction
- Textbook
- Topics Covered
- Class/Assigned Readings
- Office Hours
- Course Outcomes
- Lectures
- Homework
Introduction
Moore’s Law expanded the use of general-purpose computer components into every niche of our lives. Expansion into new markets reduced component costs and supported a continuous cycle of new architecture enhancements. These enhancements combined with transparent clock frequency increases to provide a periodic cycle of exponential performance increases that characterized the era of Moore’s Law. The ending of Dennard scaling ended the era of exponential performance increases and Moore’s Law continues to slow. The recent rise of computationally demanding machine learning and big data analytics applications combined with the slowdown of performance increases to usher in a new era of domain specific architectures as well as domain specific languages. This course will study both the economic as well as technical changes that are driving a change from general purpose to custom and application specific accelerators. The course will introduce students to domain specific accelerator architectures including but not limited to systolic arrays, array processors, in/near memory, and neuromorphic computing models, NVM analog accelerators, and application driven custom designed accelerators. Materials for this course will be drawn from the literature. Students will be required to make presentations and engage in a semester project.
Textbook
Materials for this course will be drawn from the literature. Students will be required to make presentations and engage in a semester project. Supporting and Background Materials will be drawn from Computer Architecture. A Quantitative Approach. Sixth Edition, by David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers, Inc., 2019.
Topics Covered
- The rise and decline of Moore’s Law
- Understanding the requirements of Machine Learning
- SIMD Architectures
- Vector Processors
- Array Processors
- Graphics Processor Units (GPUs)
- Systolic Arrays
- Case Studies
Class/Assigned Readings
Lecture meets M/W/F 9:40 - 10:30 JB Hunt 236 Readings posted for a week represent the material that will be covered for that week. Part of your preparation for the week is to have performed a first reading of the material in order to familiarize yourself with the topics that will be covered.
Office Hours
- Professor: David Andrews M-W-F 2:00 - 2:50 JBHT 527
Course Outcomes
- Knowledge of the history and social impact of high performance computing
- Knowledge of Computer Architecture
- Ability to apply knowledge of digital logic and computer organization to the design of a computer system
- Students are required to apply mathematics in the evaluation of the performance of a computer
- Students are required to understand the architecture of a domain specific accelerator